1/f noise reduction


Researcher : Wel, A.P. van der.

Supervisor(s) :

Project Duration :  Sept 1999 - 2003

Project homepage : http://jive.el.utwente.nl/Home/NoiseReduction/


Project Description

Charge transport in semiconductor devices is fundamentally accompanied by noise, which limits the signal processing capabilities of electronic circuits. Apart from "white" thermal noise, MOS transistor are notorious for their 1/f noise (its magnitude is inversely proportional to frequency). This noise contribution becomes stronger with decreasing MOS device sizes and is hence of increasing concern. Moreover, the effect of 1/f noise is not confined to low frequencies as it is up-converted to Radio Frequencies (RF) in electronic circuits like oscillators and mixers. Hence the modelling of 1/f noise and circuit techniques to reduce its effect are important, and are likely to become even more important in the future. In one of our previous research projects on phase noise in CMOS ring oscillators, an anomalous low 1/f noise contribution was observed. This could not be explained by existing noise models. With a new measurement setup we were able to show that the power density of 1/f noise in MOSFETs decreases anomalously if the transistors are switched off periodically ("switched bias conditions"). Later, we found that this effect has been observed before in 1991 in a weaker form. However, no reports on circuits exploiting the effect have been found and we seem to be the first to explore it. Recently, we showed that the effect helps to reduce the phase noise CMOS oscillators.

The aim of this project is to develop circuit techniques that exploit the physical effect of noise reduction by switched biasing.

Several researchers and designers from industry expressed their interest in the project and will monitor the utilisation aspects.